Memory devices such as Flash devices are typically required to store data with high reliability, i.e., to enable data retrieval with a low error rate. Low error rates are achieved, for example, by encoding the stored data with an Error Correction Code (ECC).
For example, U.S. Patent Application Publication 2009/0177931, whose disclosure is incorporated herein, describes memory devices and/or error control codes (ECC) decoding methods. A memory device may include a memory cell array, and a decoder to perform hard decision decoding of first data read from the memory cell array by a first read scheme, and to generate output data and error information of the output data. The memory device may also include a control unit to determine an error rate of the output data based on the error information, and to determine whether to transmit an additional read command for soft decision decoding to the memory cell array based on the error rate. An ECC decoding time may be reduced through such a memory device.
U.S. Pat. No. 8,122,323, whose disclosure is incorporated by reference, describes a method, apparatus, and system for dynamic adjustment of an error control coding (ECC) code rate. In one embodiment, a code rate may be changed from a first code rate to a second code rate in response to a change in a bit error rate.